Conventional memory controllers train an internal circuit that synchronizes a clock signal to information received from memory chips when the memory chips are in a “delay lock loop (DLL)-on” mode of operation and in a “DLL-off” mode of operation. The training for the different memory modes means dedicated hardware and additional complexity in the memory controllers to account for each mode. Designs of the memory controllers also commonly implement different training processes for each memory mode resulting in more dedicated hardware per mode.
It would be desirable to implement synchronization after a memory mode switch.